1. Technical Field
The present invention generally relates to a method of fabricating a semiconductor device. More particularly, the present invention generally relates to a method of forming a contact in a capacitor over bitline (COB) structured semiconductor device.
A claim of priority is made to Korean Patent Application No. 2004-1966, filed on Jan. 12, 2004, the disclosure of which is hereby incorporated by reference.
2. Discussion of Related Art
Higher integration in semiconductor devices has resulted in a decrease in a memory cell area. Accordingly, the cell size for a DRAM has reduced to 1.5 μm2 or less. For example, the reduction has been accomplished by reducing the distance between conductive layers in the cell unit. In accordance with the design rules, the distance between gate electrodes is equal to or less than a minimum feature size. A contact between a bit line and a drain region (bit line contact or direct contact), and a contact between a storage electrode and a source region (storage node contact or buried contact) have also been reduced to the minimum feature size.
As such, with the higher integration of the semiconductor device, the distance between the contact and adjacent interconnection lines has been reduced, and an aspect ratio of the contact hole has increased. A contact hole connects a lower interconnection line and an upper interconnection line. However, manufacturing reproducibility using a photolithography process to form contact holes is difficult. In addition, there are process limitations. Therefore, a self-aligned contact (SAC) method using insulating layers with different etch selectivity have been studied.
In a capacitor over bitline (COB) structure, if a capacitor is formed after the formation of a bit line, it is necessary to form a storage node contact to connect a storage electrode of the capacitor between bit lines and an active region of a semiconductor substrate. If the design rule is 0.2 μm or smaller and the storage node contact is a contact plug, a short may occur between the storage node contact and the bit line.
A conventional SAC method to prevent shorts between the storage node contact and the bit line is disclosed, for example, in U.S. Pat. No. 5,879,986. A silicon nitride layer is deposited after the forming a bit line. The silicon nitride layer is patterned to form spacers on the upper surface and the sidewalls of a bit line to prevent shorts between the bit line and a storage node contact. A silicon oxide layer is buried between the bit line, and then a contact hole is formed.
However, this conventional method has several problems.
First, if the distance between the bit lines is reduced, the overall thickness of the silicon oxide layer formed between the bit lines increases and the aspect ratio increases. During the etching process, the silicon nitride layer formed on the sidewalls of the bit line may be overetched or damaged, therefore, causing a short between the bit line and the storage node contact.
Second, if the silicon nitride spacers on the sidewalls are too thick, a void may form when the oxide layer is buried or it may be difficult to form the contact hole. These problems causes contact failures.